A VLSI architecture for an 80 Gb/s ATM switch core
Per M. Andersson, C. Svensson · 2002
A new ATM switch core architecture for single chip implementation is proposed The two main constraints, I/O capacity and buffer memory capacity are addressed by combining the speed capability of bipolar and the complexity capability of CMOS in a BiCMOS process. A single chip throughput of 8*10 Gb/s with very low cell loss (through a large shared buffer) is anticipated.