Testability of AND-EXOR logic vs. AND-OR logic
Luis Parrilla, Julio Ortega, A. Lloris · 2002
The extensive use of new programmable logic devices as FPGAs in the design of digital systems has motivated a great interest in AND-EXOR logic. The advantages of this logic rest on both the lower number of gates required with respect to the usual AND-OR implementation of digital circuits and the ease of the test pattern generation for some AND-EXOR structures. Nevertheless, no evidence has been presented regarding the advantages of AND-EXOR minimal forms with respect to AND-OR logic in the problem of test generation. The present paper compares the number of test patterns required for testing switching functions which are implemented by AND-OR and AND-EXOR minimal expressions, respectively. Conclusions about the situations in which it is more advantageous to use one or the other logic are established from the analysis of these results.