Minimally redundant parallel implementation of digital filters and vector scaling
K. Muhammad, Kaushik Roy · 2002
We present a computation reduction technique which can be used to obtain multiplierless implementations of digital filters without altering their frequency response. The ideas presented are also directly applicable to multiplication of vectors by scalars. The main idea is to expand computation space and reorder computation to maximize computation sharing. It is shown that the reordering problem can be formulated using a graph in which vertices represent coefficients and edges represent resources required in a computation involving the coefficient. The multiplierless solution is obtained by solving a set cover problem on the vertices in the graph. A simple polynomial run time algorithm based on a greedy approach is presented and it is shown that even for large filters (/spl ges/600 taps) less than 1 adder per coefficient can be obtained using the presented methodology.