Hybrid media-processor core for natural and synthetic video decoding
Hideyuki Fujishima, Yusuke Takemoto, Tomokazu Yoneda, Takao Onoye, Isao Shirakawa · 2003
The present paper describes two hybrid VLSI modules dedicated to MPEG-4 natural/synthetic video decoding, which are to be incorporated into an MPEG-4 based media-processor. One is matrix-vector multiplier, which can perform the matrix-vector multiplication both in the inverse discrete transform and in the geometrical transformation of three dimensional computer graphics. Another is image mapper, which can be used commonly for the motion compensation of natural video objects and for the texture mapping of synthetic video objects. The implementation result shows that these modules have been integrated with the use of 440 k and 110 k transistors, respectively. Both modules can operate at 20 MHz or less.