A divider-multiplier high level synthesis library element for DSP applications
V. Rodellar, M.A. Sacristan, Sophia Alvarez, Antonio Francisco Díaz, Virginia Peinado, Pedro Gómez‐Vilda · 2002
In this paper a divider-multiplier reusable library cell is presented. The division is implemented by means of an algorithm based on successive multiplications. The resulting structure uses a fixed-point format and two's complement arithmetic for operands of any size. It is coded with the VHDL synthetizable subset for the Synopsys/sup TM/ Behavioral Compiler. The performance results in terms of area and time delay for different operand sizes and technologies are presented and discussed.