A Hard Decision LDPC Decoder Implementation for Error Correction of NAND Flash Memory
Jieun Lim, Junho Cho, Wonyong Sung · ICEIC : International Conference on Electronics, Informations and Communications · 2008
We implemented a decoder for low-density paritycheck (LDPC) codes intended for NAND flash memory error correction. Since the input is given as a binary valued signal, a hard-decision bit flipping based decoding algorithm is used. To simplify the hardware, a circular shiftregister based partially parallel decoding architecture is employed. With this architecture, it is very easy to increase the throughput or reduce the power consumption by raising the parallel factor. The implemented decoder, which employs a (4161, 3431) projective geometry-based LDPC code, operates at 400 Mbit/s throughput with the parallel factor of 32. Synthesized using a 0.25㎛ CMOS technology, the proposed decoder consumed 208 ㎽ with 2.5 V supply.