Delay-power product simulation results for one-hot residue number system arithmetic circuits
William A. Chren, C.H. Brogdon, D. Andrevska · 2002
We present Spice simulations which verify previous analytical estimates of the delay-power product of One-Hot Residue adders and multipliers. These simulations show greater than a 50% reduction in the product below binary adders and an order of magnitude reduction for multipliers. Analytical models are derived from these results. They can be used to predict performance for larger moduli.