A high performance systolic chip for spelling correction
Dominique D. Lavenier · 2003
The author presents a fully integrated co-processor for accelerating the character string comparison involved in the spelling correction process. The chip is based on a truncated 2-D systolic array of 69 processors and is able to perform up to 1.3 Gops. Real time spelling correction is possible on very large vocabularies since dictionaries of 200000 items can be processed in only 0.1 second. The LVLSI chip has been designed in a 1.5 mu m CMOS technology. It integrates 270000 transistors on a 10 mm*12 mm silicon area (without pads).>