A priority forwarding router chip for real-time interconnection networks
Toda, Nishida, Takahashi Takahashi, Kazunori Yamaguchi · 1994
The design and performance of a priority forwarding router chip are presented. The chip has four input and four output ports, employs clock-synchronized packet switching, and facilitates 32-bit priority arbitration by means of a priority forwarding scheme that prevents priority inversion and enables accurate priority control within a network. Packets are of a fixed size, each having three 38-bit segments. Each input port has an 8-packet priority queue that enables virtual cut-through switching and pipelined-simultaneous output to at most three different output ports. The chip has two 25-ns pipeline stages and its data transmission rate is 190 MByte/s per port. Clock level simulation shows that the chip can attain high throughput, 9 GByte/s and 34 GByte/s at 64-node and 256-node omega networks with random communication, and excellent real-time performance. Very small laxities are required for in-time delivery of all input packets where the packets exhibit a degree of deadline distribution.>