Delay test of chip I/Os using LSSD boundary scan
P.S. Gillis, Frank Woytowich, K. McCauley, U. Baur · 2002
This paper describes a novel design-for-test (DFT) concept for I/O delay testing while contacting very few pads, using boundary scan and new test-generation software. In production testing of the IBM System/390 Generation 3/sup TM/ and several ASIC chips, these patterns uncovered unique manufacturing defects.