A technique to reduce power and test application time in BIST
Debjani Ghosh, Swarup Bhunia, Kaushik Roy · 2004
Abstract — Increased switching activity during testing causes substantial increase in power dissipation. This paper presents an efficient test application procedure for reducing power dissipation in test-per-scan BIST as well as the test application time, while maintaining the fault coverage. Experiments on ISCAS89 benchmarks show promising results- up to 51.8 % (63.1%) peak power reduction and an average energy saving of 36.3 % (62.3%) in the combinational logic (scan chain) for three partitions.