A low-power system-on-chip for the documentation of road accidents
L. Bolcioni, R. Guerrieri · 2002
The design flow and implementation of a system-on-chip for the documentation of road accidents is presented. Key features of the system are the implementation, on a programmable architecture, of a compression algorithm capable of encoding up to 15 black & white QCIF frames/s, and the computation of a digital signature performed every frame which is applied to the encoded bitstream certifying the source of the video sequence. The system has been implemented in 6/spl times/6 mm/sup 2/ on a 0.25 /spl mu/m, 6-metal standard-cell CMOS technology and works at 40 MHz, 2.5 V power supply. The adoption of IP reusable cores has allowed the system to be completed in 1 man-year time from idea to physical implementation.