Notice of Violation of IEEE Publication Principles Area efficient TAM controller and wrapper design for embedded cores
G. Rohini, S. Salivahanan · International Conference on Control and Automation · 2009
IEEE 1500 is a standard under development which intends to improve ease of test reuse and test integration with respect to the core-based SoCs. The subject paper proposes developing test environment and test methodologies for digital embedded cores based system-on-a-chip (SoC). The digital cores used in the study were constructed from ISCAS 85 combinational and ISCAS 89 sequential benchmark circuits. The wrapper that separates the core under test from other cores is assumed to be IEEE 1500-compliant. The test access mechanism plays an important role in transporting the test patterns to the desired core and the core responses to the output pin of the SoC. The faults were injected using a fault simulator that generates tests for the core. The cores and test access mechanism were described using VHDL. The test access mechanism (TAM) provides the connection between the test sources, cores, and test sinks, and is crucial in any SoC design. The outcome was the fault coverage of all the cores being tested. Area overhead and power consumption are taken into account in our scheme. Some experiment results based on a sample SoC are reported, showing the effectiveness of the proposed approach in terms of area overhead.