High-level testing for digital VLSI-a survey
Teresa Riesgo, Javier Uceda, Fernando Aldana · 2002
This paper presents a survey of the most important high-level test approaches for digital VLSI circuits. The denomination high-level is applied to every technique that considers not only structural aspects of the circuit, but also behavioral or functional information. The test problem for complex VLSI circuits is posed and solutions coming from high-level considerations are described. The selection of references has been made choosing those works that have contributed to an original solution within the field. A preview of the future trends and some conclusions are extracted at the end.>