Robust LSI architecture and its high speed viterbi decoder
Yasuyuki Hatakawa, Yoshikazu Miyanaga · 2004
This paper presents a robust LSI architecture which avoids all malfunctions and makes the system work correctly. The proposed architecture realizes a robust design only by using small overhead since it reconfigures all circuits to eliminate malfunctions by using switches. This method has the advantages of a conventional fault tolerant system. As one of these advantages, all resources are effectively used in comparison with conventional fault tolerant systems which usually apply duplicated modules and thus uses many redundant modules. In addition, this paper introduces a robust architecture of the high-speed Viterbi decoder as an example and evaluates the validity of the proposed architecture.