Hardware implementation of genetic algorithms using FPGA
K.S. Tang, L. Yip · 2004
In this paper, a hardware implementation of genetic algorithm using field-programmable gate arrays (FPGAs) is described and implemented. Such development can greatly improve the speed of genetic algorithm by the hardware parallel and pipelined architectures. In our design, various configurations of parallelization are available with a PCI board based design, which further helps in forming a fast optimization tool for real-world applications.