Synthesis for FPGAs: an overview
B.K. Fawcett · Proceedings of WESCON '94 · 2002
An increasing number of FPGA users are adopting top-down design methodologies using HDLs and logic synthesis. While not a panacea, rapidly-improving synthesis technology is starting to fulfil its promise of enabling efficient, technology-transparent, high-level design. FPGA synthesis tools will continue to improve and evolve. The goal is a top-down design methodology that encompasses design creation, analysis, and physical implementation in a seamless environment, thereby improving designer productivity and increasing silicon efficiency.>