Special Purpose Hardware for Design Rule Checking
Larry Seiler · CalTechCONF (Cal Tech) · 1981
Special purpose hardware can significantly increase the speed of integrated circuit design rule checking. The architecture described in this paper uses four custom chips to implement a raster scan DRC algorithm. It allows the use of 45° angles and can be programmed to check a wide variety of design rules involving an arbitrary number of layers. A shrink/expand operation allows the use of rasterization grids that are small relative to the minimum feature size. Using the Mead/Conway NMOS design rules and assuming a grid size of 1/2λ or 1/4 the minimum transistor width, this hardware can completely check a 3000λx3000λ layout in under a minute, if the input data can be provided quickly enough.