VLSI design of the shuffle-exchange network for 2D fast transforms
K.-A. Wen, Pao-Ying Cheng, Ruey-Yih Lin · 1993 IEEE International Symposium on Circuits and Systems · 2002
A pipelined shuffle-exchange network is proposed as a generalized 2D orthogonal transform with flexible transform lengths. The 16 /spl times/ 16 points 2D discrete cosine transform (DCT) processor is chosen as the target design for its applicability in video processing. It is constructed in a modulized radix-4 pipelined structure and is implemented with high data rate and low hardware cost. According to the circuit simulations with 1.2-/spl mu/m standard cell technology, the processing throughput of this DCT circuit can be 40 MHz. Extensibility for various indices and transform lengths are discussed. A number of orthogonal transform algorithms are implemented in the shuffle-exchange network with the same throughput rate.>