Automatic validation test generation using extracted control models
Rob Sumners, J. Bhadra, Jacob A. Abraham · 2002
We present a procedure for the automatic generation of tests covering control states of a sequential circuit. The procedure consists of extracting a control model of the circuit under test and then using this model to guide the search for concrete executions or witnesses. We present results of experiments using the procedure on a communication chip from industry as well as an implementation of the ARM 2 processor.