Collision detection VLSI processor for intelligent vehicles based on efficient coordinate transformation scheme
Masanori Hariyama, Michitaka Kameyama · 2002
This paper describes a high-performance VLSI processor for the collision detection of intelligent vehicles. In the collision detection, high-computational power is essential in not only coordinate transformation but also matching operation between vehicle and obstacle pixels. In the processor, a content-addressable memory is introduced to store vehicle pixel information, so that the matching operation is drastically accelerated. Since vehicle pixel information is predetermined and not changed, the high-performance CAM (content addressable memory) based on a ROM cell is proposed. A parallel and pipelined architecture for the high-speed coordinate transformation is also proposed based on two-dimensional vector rotations and matrix multiplications.