In troducing Semi-programmable Hardware to a Real High-Level Synthesis Tool
Akira Yamawaki, Seiichi Serikawa, Masahiko Iwane · 2010
The semi-programmable hardware is a design-level hardware architecture residing on the pass where C program with memory access is con- verted to hardware. The SPHW realizes the mem- ory access controller and buffer by writing the soft- ware program and parameters respectively. Com- pared with the cases that use only HDL, the SPHW which can design the efficient memory controllers at C-level abstraction reduces the development time sig- nificantly. In addition, the SPHW shows the compa- rable performance compared to the HDL hardware containing the custom memory controller even if it is written at high-abstraction in the SPHW. In gen- eral, the high-level synthesis tool whose design entry is C program is often used to reduce the burden de- signing the data processing hardware. However, the SPHW has not been introduced into any HLS tech- nology yet. This paper develops the true C level- design environment including the SPHW as the data processing hardware on a real commercial HLS tool, Handel-C. By using the SPHW providing the register- based data interface to the data processing hardware, we demonstrate that the HLS tool can easily write the hardware accessing to the memory in C language. This is because this interface hides the detail of the memory devices and the memory access patterns, by providing the data processing hardware with the sim- ple stream data. For hiding memory access latency, the simple software-pipelining can be applyed to the memory access program and parameters of the buffer. Consequently, the designer can realize the data pro- cessing hardware with data-prefetching mechanism at the complete C-level design entry.