Reducing dynamic power and leakage power for embedded systems
Yun Cao, Hiroto Yasuura · 2003
This paper presents a system-level technique for embedded processor-based systems targeting both dynamic power and leakage power reduction using datapath width optimization. By means of tuning the design parameter, datapath width tailored to a given application requirement, the processors and memories are optimized, resulting in significant power reduction, not only for dynamic power but also for leakage power. In our experiments with several real embedded applications, power reduction without performance penalty is reported ranging from about 14.5% to 59.2% for dynamic power, and 21.5% to 66.2% for leakage power.