An intelligent deflection router for networks-on-chip
Martin Radetzki, Adán Kohler · Workshop on Intelligent Solutions in Embedded Systems · 2009
Future manycore systems-on-chip will employ packet-switched, multi-hop interconnection networks-on-chip (NoC). In order to cope with disturbances from, e.g., faults or local traffic overload, some degree of intelligence and adaptivity has to be built into NoC routers. They need to know about their own and their environment's fault and traffic status and take this information into account when making routing decisions. In this paper, we present an approach that selects optimized routes based on a routing cost function which includes route length, fault status, and traffic congestion all at the same time. We investigate the effect on communication performance for an implementation of deflection routing as well as the router's area complexity and compare them against traditional NoC deflection routers.