A DRAM interface coprocessor for a low-cost vector microprocessor
Richard F. Hobson, G. Li, D. Smith · 2002
We describe a 32-bit DRAM interface chip which controls 4 interleaved banks of standard commercial DRAMs with no additional glue chips. The chip performs transparent address translation on the column part of the address during the row access time. Eight zero-wait-state data streams are provided for vector data manipulation.