A microprocessor in 4 months. Development of the FHOP-microprocessor-kernel via VHDL and logic-synthesis
Dirk Jansen, T. Gieringer, F. Zimpfer · 2002
In a student project at the Fachhochschule Offenburg, the design of a small CISC-processor-kernel was created in a top-down design style using extensive VHDL and logic-synthesis. Starting from only a simple architecture idea, a complete design, tailored to the requirements of small applications, was done in only four months. The kernel has a 16 bit structure, 64 kbyte address-space, interrupt-, hold- and ready-inputs and a projected performance of about 8 MIPS. The kernel is implemented in a simple test chip and it is intended to make the kernel public available as soft- and/or hard-macro for further use in microprocessor based application specific integrated circuits (ASICs).>