Architecture of high-speed 22-bit floating-point digital signal processor
Yoshikazu Mori, T. Jufuku, Masahiro Iida, Asuka Nomura, N. Ichiura, Takahiro I. Nakamura · 2005
A high-speed floating-point DSP(MSM6992) has been successfully developed as a second-generation DSP. The DSP employs a 22-bit(16E6) floating-point data format and realizes a 100-ns instruction cycle as well as an arithmetic capability of 20- MFLOPS. Furthermore, the DSP features an excellent expandability and allows the expansion of both the program and data memories up to a maximum of 64K words. In addition, the DSP enables flexible system constructions, including multi-DSP systems. The DSP is implemented by a 2µm CMOS process and contains 125K transistors within a single chip. The dimensions of the chip are 12.7 × 10.6mm2and its power dissipation is 400mW. The chip is packaged in a 132-pin PGA. This paper describes the architecture of the high-speed floating-point DSP and its VLSI implementation.