Relaxation methods for analogue fault simulation
Mark Zwoliński · 2002
The fault simulation of analogue circuits is an inherently difficult problem because of the lack of a simple fault model and because analogue simulation is itself slow. This paper describes a technique in which faulty and fault-free circuits are simulated together, such that if the terminal voltages of an active device are the same for the faulty and fault-free circuit, the model values calculated for the fault-free simulation are reused in the faulty simulation. A simple example is given in which it is shown that some savings in the CPU time are possible. Suggestions for further development of the algorithm to give substantial CPU savings are given.