Embedded memories in a 32 bit high performance microcontroller
Alfred Eder · 2002
In recent years, there has been a constant demand for higher package pin counts due to higher chip complexity offered by increasingly sophisticated semiconductor technology. Microprocessors and telecommunication chips were some of the most active driving forces. This paper describes the exact opposite: approaches from the design side to tackle the pin count problem to actually reduce the demand on pin counts. Microcontrollers, in contrast to microcomputers, have almost all memory on-chip. However, with the newly created computing power of a 32 bit processor, the demands on memory, and especially on instruction memory, also increased. In most next generation applications, the expected memory requirements exceed affordable chip sizes if the memory is made from FLASH or SRAM. Embedded DRAMs are used to obtain the required bit density and low power consumption. Since internal wires are no big concern, a wide bandwidth from memory to core supports a full context switch in typically two cycles. The maximum data transfer rate is 2.4 GB/s in this case. Caches are used to compensate for poor DRAM performance in random access mode.