A video codec chipset for wireless multimedia networking
Stephen Molloy, Rajeev Jain, K. Nishibori · 2002
This paper describes a three-chip encoder/decoder for two-way video communications in a low-bit rate wireless environment. The chipset performs 2D and 3D wavelet transforms, scalar quantization, run-length/Huffman coding and bitstream formatting/parsing with fewer than 250 K total transistors. The codec provides high-quality video at bitrates between several megabits per second down to tens of kilobits per second, with a power consumption an order of magnitude lower than existing codecs. Robust decoding of corrupted bitstreams is enabled with a hierarchy of synchronization codewords and error concealment. The three chips include a programmable wavelet transform processor, a subband decoding processor and a subband encoding processor, occupying 36 mm/sup 2/, 42 mm/sup 2/ and 47 mm/sup 2/, respectively, in 1.2-micron CMOS.