VERIFICATION MODEL STRUCTURES FOR DIGITAL SYSTEMS DESIGN
Sergey L. Frenkel · 2003
Abstract Exponential computational complexity of digital systems formal verification algorithms excludes any possibilities of full-automatic verification of complex digital systems. On the other hand, the informal design simulation is also impractical time-consuming. Probably, the possible outcome is to form a verification strategy which, on one hand would combine both approaches, and on the other hand would include a guide to issue verifications algorithms-and-tools appropriate for a given design. It implies a characterization of both verification algorithms and design process. In fact, it means a structurization of various models of design, which are used both explicitly and implicitly during design verification activity. This paper, relying on the previous experience in testability design planning [1] as well as corrent publications in formal verification areas considers some possibilities of planning of digital systems verification activity to achieve high degree of functional verification. Key words: formal verification, design verification, digital circuits simulation.