DFT advances in the Motorola's MPC7400, a PowerPC/sup TM/ G4 microprocessor
Carol Pyron, M. Alexander, J. Golab, G. Joos, Bruce Long, Robert Molyneaux, Rajesh Raina, Nandu Tendolkar · 2003
Several advances have been made in the design for testability of the MPC7400, the first fourth generation PowerPC microprocessor. The memory array built-in self-test algorithms now support detecting write-recovery defects and more comprehensive diagnostics. Delay defects can be tested with scan patterns with the phased locked loop providing the at-speed launch-capture events. Several methodology and modeling improvements increased LSSD stuck-at fault test coverage. Design for manufacturability enhancements provide better tracking of initial silicon and fuse-based memory repair capabilities for improved yield and time-to-market.