Perspective on BiCMOS
Thin Sek Wong · 2003
The objective of Hi-BiCMOS is to combine speed performance approaching that of ECL and integration density approaching that of CMOS. A high-performance 1.3- mu m BiCMOS technology and its applications to ASICs (application-specific integrated circuits) are described. This Hi-BiCMOS gate array contains 3072 gates and 90 input/output buffers. The inclusion of bipolar transistors enables this array to support both TTL (transistor-transistor logic) and ECL logic interfaces. A Hi-BiCMOS memory-plus-logic gate array has also been fabricated using a 1.3- mu m drawn two-layer metal silicon gate process technology. It contains approximately 10 K logic gates, 4.6 kb of triple port RAM, and 220 input/output buffers. A Hi-BiCMOS standard cell library has been developed to improve design productivity in microprocessor designs. Megacells such as ALUs, registers, ROMs, RAMs, multipliers and other macrofunctions are available as part of the macro library.>