An accurate simulation model of the ATE test environment for very high speed devices
T.P. Warwick, J. Cho, Y. Cai, B. Ortner · 2003
The following paper analyzes timing and calibration errors in digital ATE testers and suggests a simulation model for accurate correction of these errors. The paper reviews 11 potential timing errors (e.g. device interaction, test setup differences) not corrected by most calibration methods. The simple simulation model suggested corrects most of these potential errors.