Search space pruning techniques in ATPG for VLSI circuits
Michael G. Dimopoulos, Panagiotis Linardis · International Conference on Circuits · 2005
This paper presents a, common, unified approach to solve either the test sequence compaction problem or the power minimization problem during circuit testing. This approach is based on an exact Branch and Bound algorithm that exploits information from the respective problems. In particular decision making during the Branch and Bound method follows some rules devised so as to avoid unnecessary choices and thus reducing the search space. Experimental results that are presented, comparing the proposed algorithm with other solvers from literature, show the effectiveness of the proposed method.