An integrated processor for adaptive and parallel algorithms
M. Cand, Patrice Le Scan, A. Roset · 2005
The architecture and some basic applications of a single-chip software-programmable digital signal processor are presented. This NMOS 3.5 um silicon gate circuit is well-suited for adaptive algorithms and some input and output features allow easy implementation of multiprocessing architectures using several chips. These I/O ports are designed to transfer data serially or through an 8-bit bus. Their main feature is control of an internal program or transfer of instructions from an external memory without any loss of speed. This circuit incorporates a 16×16 bit hardware multiplier, a powerful unit to compute the addresses of two 128×16 bit RAMs and a 32-bit arithmetic and logical unit with accumulator and stack, all of which are connected by two data buses (16 and 25b wide). Either 16- or 25- bit words can be processed using this circuit.