A systolic parallel multiplier over GF(3/sup m/) using neuron-MOS DLC [down-literal circuit]
Byoung Hee Yoon, Sung Il Han, Young-Hee Choi, Jong-Hak Hwang, Hyeon-Kyeong Seong, Heung Soo Kim · 2004
In this paper, a parallel input/output modulo multiplier, which is applied to the AOTP (all one or two polynomials) multiplicative algorithm over GF(3/sup m/), has been proposed using a neuron-MOS down-literal circuit in voltage mode. The three-valued input of the proposed multiplier is modulated by using a neuron-MOS down-literal circuit and the multiplication and addition gates are implemented by the selecting of the three-valued input signals transformed by the module. The proposed circuits are simulated with the electrical parameter of a standard 0.35 /spl mu/m CMOS N-well doubly-poly four-metal technology and a single +3 V supply voltage. In the simulation result, the multiplier shows 4 /spl mu/W power consumption and 3 MHz sampling rate and maintains a output voltage level within /spl plusmn/0.1 V.