Synthesizing massive parallel simulation systems to estimate switching activity in finite state machines
W.W. Bachmann, Sorin Alexander Huss · 1997
This paper presents a methodology for automatic generation of massive parallel simulation systems to estimate the power consumption of sequential CMOS circuits. Based on a high level description of Finite State Machines C++ simulator code is being generated to estimate the power consumption of a CMOS based implementation. From a symbolic FSM description, a Monte Carlo simulation is used to estimate the average switching activity of all circuit components exercised according to user-supplied modelling parameters. Automatic generation of high parallel simulation systems with minimal communication between simulator instances as proposed in this paper allows the use of a wide range of target systems ranging from workstation to supercomputer. Due to the complexity of modern integrated circuits the use of massive parallel simulation systems up to several thousand microprocessors allows a highly efficient simulation of very large sequential circuits. Synthesizing massive parallel simulation systems to estimate switching activity in finite state machines Werner W. Bachmann , and Sorin A. Huss oo † Department of Computer Science, Integrated Circuits and Systems Laboratory Darmstadt University of Technology Alexanderstr. 10 64283 Darmstadt, Germany [email protected] †† Department of Computer Science, Integrated Circuits and Systems Laboratory Darmstadt University of Technology Alexanderstr. 10 64283 Darmstadt, Germany [email protected] Abstract This paper presents a methodology for automatic generation of massive parallel simulation systems to estimate the power consumption of sequential CMOS circuits. Based on a high level description of Finite State Machines C++ simulator code is being generated to estimate the power consumption of a CMOS based implementation. From a symbolic FSM description, a Monte Carlo simulation is used to estimate the average switching activity of all circuit components exercised according to user-supplied modelling parameters. Automatic generation of high parallel simulation systems with minimal communication between simulator instances as proposed in this paper allows the use of a wide range of target systems ranging from workstation to supercomputer. Due to the complexity of modern integrated circuits the use of massive parallel simulation systems up to several thousand microprocessors allows a highly efficient simulation of very large sequential circuits. This paper presents a methodology for automatic generation of massive parallel simulation systems to estimate the power consumption of sequential CMOS circuits. Based on a high level description of Finite State Machines C++ simulator code is being generated to estimate the power consumption of a CMOS based implementation. From a symbolic FSM description, a Monte Carlo simulation is used to estimate the average switching activity of all circuit components exercised according to user-supplied modelling parameters. Automatic generation of high parallel simulation systems with minimal communication between simulator instances as proposed in this paper allows the use of a wide range of target systems ranging from workstation to supercomputer. Due to the complexity of modern integrated circuits the use of massive parallel simulation systems up to several thousand microprocessors allows a highly efficient simulation of very large sequential circuits.