VLSI implementation of Mallat's fast discrete wavelet transform algorithm with reduced complexity
Yuanbin Guo, Hongzhong Zhang, Xuguang Wang, Joseph R. Cavallaro · 2002
This paper proposes a novel VLSI architecture to compute the DWT (discrete wavelet transform) coefficients using Mallat's algorithm with reduced complexity. We studied the commonality embedded in the mirror low-pass and high-pass filters of the algorithm and use a PLA as an address generator (PAG) to load the data for cascaded FIR computation. By using an embedded downsampling process in the control signal design, we reduced the complexity by saving storage and computation. The prototyping design is implemented and fabricated using the AMI 1.5 micron CMOS process through the MOSIS service.