A High-Throughput Low-Complexity Radix- $2^{\textbf {4}}$ - $2^{\textbf {2}}$ - $2^{\textbf {3}}$ FFT/IFFT Processor With Parallel and Normal Input/Output Order for IEEE 802.11ad Systems
Chao Wang, Yuwei Yan, Xiaoyu Fu · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2015
This brief presents a high-throughput low-complexity 512-point fast Fourier transform (FFT)/inverse fast Fourier transform (IFFT) processor for IEEE 802.11ad standard aiming at the wireless personal area network applications. To reduce the complexity of twiddle factor multiplication, the radix-24-22-23FFT algorithm is devised. To achieve the throughput of 1.76 GS/s (which is normalized as eight samples/clock) and meet the frame format of single carrier as well as orthogonal frequency division multiplexing physical layer that no interval is inserted between any two 512-length data blocks in a frame, the mixed-radix multipath delay feedback structure is adopted to support the continuous data How. Moreover, we propose a novel reorder scheme to support parallel normal-order output data How continuously, which demands only a single-RAM-group, i.e., 512-word memory size with very simple control logic. Overall, the whole FFT/IFFT processor is high throughput and area efficient, and the back-end simulation results show that the core area of the FFT processor is 1.69 mm2in Silterra 0.13 μm process.