A hardware reduced multiplier for low power design
Kwang Hyun Lee, C.S. Rim · 2002
In this paper, we proposed a hardware reduced multiplier for DSP applications. In many DSP applications, all multiplier output bits were not used, but only upper bits of output were used. Kidambi [1995] proposed a truncated unsigned multiplier for this idea. In this paper, we adopt this truncation scheme for a Booth multiplier which can be used in real DSP systems more efficiently. Also, our truncated Booth multiplier guaranteed 0 input to 0 output that was not provided in previous papers. Truncated Booth multiplier reduced area by about 37.48% and power consumption by about 44%.