A codebook, distribution and comparator (CDC) chip architecture for real-time image coding
K. Dezhgosha, M.M. Jamali, Subhash C. Kwatra · 2002
A VLSI architecture for real-time high-quality coding of color TV images at a fixed bit rate of 1.12 BPP is developed. The architecture exploits pipeline/parallel processing an don-chip memory to partition a large codebook into smaller on-chip subcodebooks. The architecture is capable of real-time processing of 480*768 pixels per frame with a refreshing rate of 30 frames/s. A floorplan for the CDC chip is developed.>