CMOS cell base implementation of the SPARC architecture
S.T. Wang, Shinn-Juh Lai, J. Chou, H.Y. Tarn, Chia-Wei Chang, Shin-Wu Tung, J.Y. Ray, J.Y. Kuo, L.M. Yang · 2002
Presents an overview of the TA53017 processor which is the first implementation of the 32-bit RISC based scalable processor architecture (SPARC) CPU chip. The TA53017 (Integer Unit) was fabricated with TSMC's 1.2 um double-metal CMOS technology and completed in the CCL/ITRI's hierarchical cell-based design environment. It operates at a clock rate of 25 MHz and delivers an average performance of 10-15 MIPS, with an external cache and a floating-point coprocessor.>