Destructive-read random access memory system buffered with destructive-read memory cache for SoC applications
B.L. Ji, Seiji Munetoh, Chorng-Lii Hwang, Matthew R. Wordeman, Toshiaki Kirihata · 2004
This paper describes a novel random access memory system. The system is based on a destructive-read memory buffered by a destructive-read memory cache for hidden write back. SRAM comparable random access cycle time (tRC) is achieved, as tRC of the architecture is limited only by the destructive-read time of the memory array. By using a DRAM array as cache, the silicon area is reduced by about 25% from SRAM-cache system. Write back algorithms have been proved by mathematical models, and confirmed by simulations.