A systolic approach to multistage interconnection network design
C.-H. Chen, Laxmi Narayan Bhuyan · 2003
An algorithm to map a multistage interconnection network (MIN) onto a systolic array is developed. The algorithm provides a systematic approach that lays out a cube MIN in a compact area. An area-delay analysis is presented and is compared with that of a crossbar. It is shown that the cube MIN performs better than crossbar in both area and delay.>