Fault tolerant characteristics of the linear array architecture for WSI implementation of neural nets
Fausto Distante, M.G. Sami, Renato Stefanelli, Giancarlo Storti Gajani · 2002
A novel digital architecture supporting implementation of feedforward, multilayered artificial neural networks is presented. Based on a switched bus array philosophy, particular care is taken to minimize area requirements while maximizing throughput and parallelism. The architecture is well suited to support, with minimal additional changes, fault/defect tolerance with respect to faults located in the PEs (processing elements), switches, or buses.>