High performance BiCMOS circuit technology VLSI gate arrays
Gallia, Yee, Chau, Wang, Davis, Moore, Chas, Lemonds, Eklund, Havemann, Bonifield, Graham, Pozadzides, Shah · 1989
This paper discusses the design and technology for a high density, full BiCMOS channelless gate array. A gate delay of 360ps lor a 0.4pf load has been achieved on a 106k gate (2- input NAND equivalent) test chip.