Sum-subtract fixed point LDPC decoder
Leonardo J. Arnone, Carlos Arturo Gayoso, C. M. Gonzalez, J. Castiñeira · Latin American Applied Research - An international journal · 2007
In this paper a low complexity loga- rithmic decoder for a LDPC code is presented. The performance of this decoding algorithm is similar to the original decoding algorithms, introduced by D. J. C. MacKay and R. M. Neal. It is a simplified algo- rithm that can be easily implemented on program- mable logic technology such as FPGA devices be- cause of its use of only additions and subtractions, avoiding the use of quotients and products, and of float point arithmetic. The algorithm yields a very low complexity programmable logic implementation of a LDPC decoder with an excellent BER perform- ance.