Scheduling of a control data flow graph
S. Amellal, Bożena Kamińska · 1993 IEEE International Symposium on Circuits and Systems · 2002
A new control and data flow graph (CDFG) model for the high-level synthesis of digital systems is presented together with a new formulation of the scheduling problem. This CDFG model generates a single graph representing both the data and the control flows of a VHSIC hardware description language (VHDL) behavioral description. The introduction of the conditional dependency edges in the graph makes it possible to implement the control constructs simply and efficiently. A branch numbering procedure is developed to allow detection of mutual exclusion among graph nodes. A new mathematical formulation of the scheduling problem is developed using an approach based on penalty weights. Typical examples are presented to demonstrate the advantages of the approach.>