Implementation of systolic multipliers and digital filters via signal flow-graph transformations
Kiamal Pekmestzi, C. Caraiscos · 2002
Massive insertion of delay elements in a one-way signal flow-graph of an FIR digital filter, and/or proper transfer of delay elements between edges in a two-way signal flow-graph lead to systolic arrays for the implementation of a serial-parallel multiplier, a bit-parallel multiplier, and an FIR digital filter. All of them are of the merged type and exhibit lower latency than existing ones, without any increase in throughput or circuitry.>